1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the invention relates to a nonvolatile semiconductor memory device of insulating-film breakdown type, in which high voltage is applied to the semiconductor elements of MOS structure, breaking down the insulating film in each element, thereby to store data in nonvolatile state.
2. Description of the Related Art
In recent years, nonvolatile semiconductor memory devices have been proposed, in which semiconductor memory elements of insulating-film breakdown type (hereinafter called e-Fuse elements) are used as memory elements. An e-Fuse element is a semiconductor element of MOS structure. Its insulating film is broken down when it is applied with a high voltage that exceeds the maximum rated value, whereby the element stores data in nonvolatile state. Thus, a nonvolatile semiconductor memory device having e-Fuse elements used as memory elements store data when the characteristics of the e-Fuse elements are irreversibly changed. By nature, this memory device can be programmed only once to store data. This is why this nonvolatile semiconductor memory device is called one-time programmable (OTP) memory. In the OTP memory, each e-Fuse element stores data “0” before its insulating film is broken down. Once the insulating film has been broken down, the e-Fuse element stores data “1,” which may be utilized.
The OTP memory described above is expected to find use in the future in various fields, such as redundancy technology for dynamic random access memories (DRAMs), tuning of analog circuits, storage of codes such as encryption keys, and storage of chip identification data (ID).
In the conventional OTP memory, each memory cell, i.e., data storage unit, comprises, for example, an e-Fuse element, a barrier transistor, a selection transistor, a sense circuit, a data resistor, and a control transistor. (See, for example, H. Ito et al., “Pure CMOS One-time Programmable Memory using Gate-Ox Anti-fuse,” Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, pp. 469-472.) The e-Fuse element is composed of a pMOS transistor. The barrier transistor is provided to mitigate the influence the high voltage applied to program the e-Fuse element imposes on the peripheral circuits and other elements. The selection transistor is a transistor for selecting the e-Fuse element. The sense circuit is used to read data from the e-Fuse element. The data resistor is configured to hold data. The control resistor is configured to hold control data that is used to program the e-Fuse element.
The e-Fuse element stores data “1” when the high voltage applied between its gate electrode and its source-drain terminal breaks down its gate-insulating film. That is, to store data “1” in the e-Fuse element, a high voltage falling outside the rated range (i.e., a voltage exceeding the maximum rated value) is applied between the gate electrode and the source-drain terminal. Therefore, the transistors other than the e-Fuse element, i.e., the barrier transistor, the selection transistor and the transistors constituting the sense circuit, are high-voltage transistors that operate at voltages higher than the voltages at which the pMOS constituting the e-Fuse element operates. In other words, the e-Fuse element is composed of a pMOS transistor than can operate at a voltage lower than the operating voltages of the barrier transistor, the selection transistor and the transistors constituting the sense circuit.
In some types of conventional OTP memories, the memory cells are integrated, forming a fuse macro (e-Fuse macro). The fuse macro is composed of, for example, a plurality of fuse blocks (e-Fuse blocks), an internal-potential generating circuit, and a fuse-macro control block. The internal-potential generating circuit generates an internal potential required in programming and sensing. Each fuse block is composed of memory cells for 64 bits and a control circuit for controlling these memory cells. The memory cells are connected in series, providing 16 stages. Thus, a fuse macro having a large storage capacity is implemented. The control block of the fuse macro operates in synchronism with a clock signal (CLK). The control block serially is configured to input program data via the data input terminal (SI) in order to write the data, and to output the program data via the output terminal (SO) in order to read the data. The control block input some other control signals, thereby controlling the sensing and reading of the program data stored in the memory cells of each fuse block of the fuse macro.
In such a fuse macro of this configuration, each memory cell includes a sense circuit provided for the e-Fuse element. Hence, the fuse macro makes it easy to design OTP memories of large storage capacity. However, the memory cells have a large size, inevitably increasing the size of the OTP memory.
To solve this problem, an OTP memory of such a type as descried below is now studied. This OTP memory has a plurality of memory cells, each composed of an e-Fuse element, e.g., pMOS transistor, and a selection transistor. These memory cells are arranged in rows and columns, forming a matrix. The gate electrodes of the selection transistors of each row are connected to the one of the paired row-selecting lines provided for the row. The node of the e-Fuse element of any memory cell of the row, which is applied with high voltage, is connected to the other of the paired row-selecting lines. One of the paired row-selecting lines is applied with a voltage that falls within the rated range of the selection transistor for selecting the e-Fuse element. The other of the paired row-selecting lines is applied with a voltage that falls outside the rated range, which is high enough to break down the gate-insulating film of the e-Fuse element. A row decoder controls the application of voltages to the paired row-selecting lines. A data line through which data can be read and written from and into the e-Fuse element is connected to a sense amplifier, a data register and a control register. The sense amplifier, the data register and the control register are provided commonly for the memory cells of each column.
Since the fuse macro is so configured as described above, the area of each memory cell can be reduced. Ultimately, the area of the fuse macro can be decreased. For example, the fuse macro described above has a fuse block, a sense-amplifier block, a register block, a row-decoder block, an internal-potential generating circuit, and control circuits. The fuse block has 32×32 memory cells arranged in 32 rows and 32 columns, forming a memory matrix. The sense-amplifier block has 32 sense amplifiers. The register block has 32 registers. The row-decoder block has 32 row decoders. In the OTP memory having the fuse macro of this configuration, too, the selection transistors, the transistors constituting the sense amplifiers and the transistors constituting the row decoders are transistors that operate at high voltage. The pMOS transistors constituting the c-Fuse elements and the transistors constituting the data registers and control registers are transistors that operate at low voltage.
As specified above, the area of the fuse macro can be reduced since a plurality of memory cells share the same sense amplifier and the like. However, the capacitance of each data line will increase if the integration degree of the OTP memory is raised. The current that flows in each memory cell programmed is not so large because it flows in the gate-insulating film that has been broken down. On the other hand, the gate width of each selection transistor is relatively large in order to supply a large current for programming. If more e-Fuse elements are connected to one sense amplifier, the capacitance of the data line will greatly increase, though the cell current remains the same. The sense time the sense amplifier requires to operate appropriately will inevitably increase.
In many cases, OTP memories of such configuration are generally used in such a manner that the data in the e-Fuse elements is detected when the system is turned on, and is thereafter transferred to a location where the data is required. The time that may be used to turn on the system depends on the type of the system. Nevertheless, the integration degree of the e-Fuse elements will be limited if it increase in proportion to the sense time required to detect the data.